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Si5040
5.2. Limiting Amplifier
The Si5040 incorporates a high-sensitivity differential limiting amplifier with sufficient gain to allow direct connection
to a transimpedance amplifier. The amplifier has a guaranteed sensitivity of 8 mVppd.
5.3. Receive Amplitude Monitor
The Si5040 limiting amplifier includes circuitry that monitors the amplitude of the receiver differential input signal
(RXDIN). The amplitude value can be read from the Peakdet register (Register 16). The receiver signal amplitude
monitoring circuit is also used in the generation of the loss-of-signal alarm (LOS).
5.4. Receiver Loss of Signal Alarm (LOS)
The Si5040 receiver generates a loss-of-signal alarm when the input signal fails to meet the selected
programmable condition for loss of signal. The programmable LOS mode is controlled in the RxlosCtrl register
(Register 10). The programmable modes are Analog Loss Of Signal (ALOS), Digital Loss of Signal (DLOS), and
Signal Quality Monitor (SQM). As shown in Figure 15, one or more of these alarm signals is logically combined into
the Receiver Loss of Signal (RX_LOS) alarm pin (Pin 3). The state of the RX_LOS alarm pin will also be reflected
in the LOS bit in the RxAlarmStatus register (Register 9). LOS may also be configured to generate an interrupt. The
status of the LOS interrupt bit may be read in the RxintStatus register (Register 5). The status of the various LOS
modes is stored in the losStatus register (Register 11).
An ALOS alarm occurs when the peak-to-peak signal amplitude on the RXDIN input is below the threshold value
set in the aLosThresh register (Register 12). The level may be set from 10 to 400 mV in 1 mV increments. The
amount of hysteresis applied to ALOS is set in the aLosThresh2 register (Register 13) up to a maximum of
“aLoSThresh+” 6 dB. The default value is “aLoSThresh+” 3 dB. The analog LOS function is enabled by setting bit 0
in the RxLosCtrl register (Register 10). Note that the peak-to-peak detector and ALOS detection are designed to
work with pseudo-random dc-balanced data band limited to <2 GHz.
A DLOS alarm occurs when the receive bit stream consists of a run length of 1s or 0s greater than the value loaded
in the RxdLosAssertThresh register (Register 17). DLOS will remain asserted until the data shows activity for a
time greater than that loaded in the RxdLOSClearThresh register (Register 18). Refer to Figure 10 and Figure 11
for algorithm flowcharts.
An SQM alarm occurs when the estimate of the receive signal quality falls below the value loaded in RxsqmThresh
(Register 26). The Signal Quality Monitor measures the magnitude of the horizontal eye opening of the received
signal. The SQM value can be read from the RxsqmValue register (Register 25). An SQM alarm will assert if the
RxsqmEn bit has been set in the RxsqmConfig register (Register 26). SQM hysteresis is set in the
RxsqmDeassertThresh register (Register 27).
CID (Continuous
Identical Digits)
Monitor
Is CID > (dLosAssertThresh *5 +2) *1024
Yes
Set dLos
Figure 10. Algorithm to Set dLOS
No
20
Rev. 1.3
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